High performance trans impedance amplifier (TIA) circuits are important building blocks for high speed data communication, such as optical chip-to-chip links at data rates beyond 20 gigabits per second (Gb/s). In order to achieve the best possible gain/bandwidth performance in complementary metal oxide semiconductor (CMOS) receivers for chip-to-chip optical interconnects, inductive peaking is generally used to extend the bandwidth and resonate out parasitic capacitance. Additional gain is often obtained by introducing larger input devices or larger resistive loads, which may reduce bandwidth. Alternatively, additional gain stages may be introduced, which consume additional power. Furthermore, as CMOS scales further into the nanometer gate length range, the transconductance and drain resistance may be reduced, which may lead to a decrease in gain.